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1

Japanese garbage management: debunking American myths

Steven M. Polan, Raymond Cachares

Journal:

Resources, Conservation and Recycling

Year:

1993

Language:

english

File:

PDF, 215 KB

english, 1993

2

[IEEE Proceedings of the 34th European Solid-State Device Research Conference - Leuven, Belgium (21-23 Sept. 2004)] Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) - Failure rate predictions for 0.35 μm Flash EEPROM memories from accelerated read disturb tests

Vermeulen, T., Yao, T., Lowe, A., Cacharelis, P., Degraeve, R., Van Houdt, J.

Year:

2004

Language:

english

File:

PDF, 260 KB

english, 2004

3

A back-biased 0.65 μm Leffn CMOS EEPROM technology for next-generation sub 7 ns programmable logic devices

Michael J. Hart, Philip J. Cacharelis, Roger D. Carpenter, David G. Tsuei, Raminda U. Madurawe, Bal S. Sandhu, Richard G. Smolen, Andrew P. Dumlao, Tim L. Garverick, Thomas McFarlane, Martin H. Manley

Journal:

Microelectronic Engineering

Year:

1991

Language:

english

File:

PDF, 240 KB

english, 1991

4

A reflective-mode EEPROM-based silicon light-valve technology

Paul Moore, Philip Cacharelis, Jerry Frazee, David Chung, Rick Luttrell, Russell Flack

Journal:

Journal of the Society for Information Display

Year:

1999

File:

PDF, 2.97 MB

1999

5

[IEEE Technical Digest., International Electron Devices Meeting - San Francisco, CA, USA (11-14 Dec. 1988)] Technical Digest., International Electron Devices Meeting - A modular 1 mu m CMOS single polysilicon EPROM PLD technology

Cacharelis, P.J., Hart, M.J., Manley, M.H., Frake, S.O., Knecht, M.W.

Year:

1988

File:

PDF, 385 KB

1988

6

A single transistor electrically alterable cell

P. Cacharelis, E. Fong, E. Torgerson, M. Converse, P. Denham

Journal:

IEEE Electron Device Letters

Year:

1985

Language:

english

File:

PDF, 324 KB

english, 1985

7

[IEEE IEEE International Solid-State Circuits Conference - New York, NY, USA (15-17 Feb. 1989)] IEEE International Solid-State Circuits Conference - A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell

Frake, S., Knecht, M., Cacharelis, P., Hart, M., Manley, M., Zeman, R., Ramus, R.

Year:

1989

Language:

english

File:

PDF, 707 KB

english, 1989

8

Electron barrier height change and its influence on EEPROM cells

Sethi, R.B., Kim, U.S., Johnson, I., Cacharelis, P., Manley, M.

Journal:

IEEE Electron Device Letters

Year:

1992

Language:

english

File:

PDF, 254 KB

english, 1992

9

[IEEE IEEE Custom Integrated Circuits Conference - Boston, MA (May 3-6, 1992)] Proceedings of the IEEE Custom Integrated Circuits Conference - A 1.0 μm BiCMOS With EEPROM Technology For Application In The Design Of Smart Analog And Mixed-signal ASIC Products

Cacharelis, P., Farrenkopf, D., Johnson, I., Manley, M., Merrill, R., Teng, C.S.

Year:

1992

Language:

english

File:

PDF, 314 KB

english, 1992